The present invention generally relates to IC-technology and more specifically the invention relates to the formation of an electrical device structures such as e.g. an inductor structure, particularly a spiral inductor structure for radio frequency (RF) applications, integrated in an integrated circuit (IC), to the electrical device structure and the integrated circuit themselves, and to a method of etching and measuring etched depth non-destructively.
The Problem Area and Known Solutions
Advanced silicon bipolar, CMOS or BiCMOS circuits are used today for high-speed applications in the 1-5 GHz frequency range, replacing circuits previously only possible to realize using III-V based technologies.
Inductor elements are often needed in high-frequency circuits building blocks like resonators and filters. An object common to all integrated technologies is to obtain inductors with high quality factors, so-called Q-values, and high operating frequencies (limited by the resonance frequency fR, at which Q has fallen to zero).
Recent advances in silicon IC processing technology have allowed inductor layouts with higher inductance per area and lower losses because of reduction of feature sizes and multilayer metallization with thick oxide to isolate the inductor from the substrate. A typical integrated inductor for 1-2 GHz circuits has inductance values in the 1-10 nH range and will occupy an area up to 500 xcexcmxc3x97500 xcexcm, which make it very large and costly to integrate. There are still considerable losses because of the resistivity of the metallization, coupling to the substrate and losses in the substrate. Inductors elements in the 1-10 nH range with Q-values higher than 15 at 1-2 GHz are hard to obtain using silicon IC-technology.
Integrated inductors are usually designed as octagonal or square spirals metal stripes 1 on an oxide 2 formed above a semiconductor substrate 3 as illustrated in FIG. 1. An equivalent circuit for such inductor structure is schematically shown in FIG. 2. The Q-value can be calculated at low frequency (where the substrate parasitic capacitances yet do not dominate the performance) as Q=xcfx89L/r (xcfx89=2xcfx80f, f being the frequency; and L and r are the inductance and the resistance, respectively, of the inductor).
Because of the capacitance Cox of the isolation material between the metallization pattern and the substrate, and the silicon substrate""s conducting properties, i.e. its capacitance Csi and resistance Rsi, see FIG. 2, the Q-value is reduced in the frequency range of interest (ranging from say a couple of hundred MHz to 10 GHz).
By using the upper conductor levels in a multilayer metallization system to design the inductor, the capacitance Cox is decreased because the inductor is further displaced from the substrate ground plane by a thick oxide. The Q-value of the inductor is consequently increased.
Another, more drastic, method is to selectively remove most of or all silicon under the inductor, see e.g. U.S. Pat. No. 5,539,241 (Abidi et al.); U.S. Pat. No. 5,930,637 (Chuang et al.), U.S. Pat. No. 5,773,870 (Su et al.); and U.S. Pat. No. 5,384,274 (Kanehachi et al.). The Cox parameter is lowered by the additional distance to the substrate created by the hole. This results in higher Q-values and higher self-resonant frequencies. The Q-value can be increased by a factor of two by such a removal in the form of a silicon etch from the backside of the substrate, giving air gaps of several hundred micrometers, but such techniques are not regarded as feasible in large scale production of silicon IC.
Solutions combining increased oxide thickness and partial substrate removal are known. In U.S. Pat. No. 5,833,299 (Merill et al.) is described a method where V or pyramidal shaped grooves are etched in the substrate, filled with oxide and planarized to form local islands with the result of a considerably increased isolation oxide thickness, compared to the rest of the circuit. On top of these islands, integrated inductors are formed.
Other methods to reduces the losses from the silicon substrate are disclosed in e.g. U.S. Pat. No. 5,742,091 (Hxc3xa9bert), where patterns of deep trenches filled with isolation material (already available in high-performance RF-IC process flows), are placed under the inductor structure to reduce the losses.
Improved techniques to remove silicon from substrate include formation of cavities in the substrate. In EP 0 971 412 A2 (Yoshida), a method is disclosed where large cavities (100 xcexcm wide) are formed in the substrate, and subsequently filled with e.g. oxide, whereafter an inductor structure is formed thereon, and the material used to fill the cavity is then removed in a final step, to create an air-filled hole in the substrate.
In U.S. Pat. No. 6,025,261 (Farrar et al.), an inductor structure is described which incorporates polymer filled cavity structures etched in the passivation layer situated under the metal pattern for the inductor and the semiconducting substrate. However, the cavity structure is only formed in the passivation layer on top of the silicon substrate, and because of the limited thickness of this layer and the lower ∈r, compared to substrate silicon, the effectiveness of this structure is probably very limited.
In microelectromechnical technology (MEM), device structures are needed that can be used as sensors for pressure, acceleration, temperature etc. These structure can also be integrated on a chip, where detection electronics can be placed. In U.S. Pat. No. 6,012,336 (Eaton et al.) is disclosed a capacitance sensor structure which includes removing part of the silicon substrate, filling it with an insulator (such as silicon dioxide), and forming a structure on top of it, serving as the sensor.
Problems with Known Solutions
A solution is needed where silicon is removed under an integrated inductor structure. It must be compatible with conventional silicon IC processing, and add a minimum of additional process steps to the existing flow. The method must also be able to remove silicon fully or partly over areas larger than 500 xcexcmxc3x97500 xcexcm, since this is approximately the size of an integrated inductor used in communication equipment at 1-2 GHz of operating frequency.
Previously described concepts, referred to as prior art, include processing which is complex and complicated or not compatible with conventional IC processing or do involve an excessive number of steps.
Other known methods include filling the etched cavity with isolating material, e.g. silicon dioxide or a polymer. The dielectric constant ∈r of these materials are indeed lower, i.e. better, than that of silicon. However, an empty cavity has the lowest dielectric constant (i.e. ∈r=1), so if no filling can be used, this will be preferred.
Yet other methods do not provide for structures including empty cavities, which are strong enough to withstand subsequent processing, i.e. formation of a multilayer metallization system, which is part of the subsequent conventional IC flow. This may be particularly relevant for larger inductor structures such as 500 xcexcmxc3x97500 xcexcm, and larger.
It is consequently an object of the present invention to provide a method in the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, for forming an electrical device structure, particularly an inductor structure, while overcoming at least some of the problems associated with the prior art.
It is a further object of the present invention to provide a structure formation method, which is capable of fabricating inductor structures, which obtain high Q-values and high resonance frequency.
It is still a further object of the invention to provide such structure formation method, which is capable of fabricating electrical device structures, including inductor structures, which are mechanically strong and durable.
It is yet a further object of the invention to provide such structure formation method, which is simple to perform, and which is compatible with conventional processing techniques.
It is in this respect a particular object of the invention to provide such method that adds a minimum of additional process steps to a conventional IC process.
These objects among others are, according to one aspect of the invention, fulfilled by a method comprising the following steps:
providing a semiconductor substrate;
forming a passivation layer above the substrate;
forming a plurality of through holes in the passivation layer;
removing semiconductor substrate material under the passivation layer by means of isotropic etching using the passivation layer provided with through holes as hardmask, thus forming a first cavity in the semiconductor substrate substantially underneath the through holes;
forming a dielectric layer on top of the passivation layer to plug the through holes, thereby creating a membrane above the cavities; and
creating an electrical device, such as e.g. an inductor, above the membrane.
Preferably, the method includes that the plurality of through holes formed in the passivation layer are dividable into a first and a second sub-group, respectively, such that adjacent through holes within a sub-group are more closely located than adjacent through holes belonging to different sub-groups; that semiconductor substrate material under the passivation layer is removed to form also a second cavity in the semiconductor substrate substantially underneath the through holes, such that the cavities are separated by a portion of semiconductor substrate material, which supports the membrane above the cavity.
Furthermore it is an object of the present invention to provide an electrical device structure, particularly an inductor structure, resulting from above said fabrication method; and an integrated circuit comprising such a structure.
According to a second aspect of the present invention there is thus provided an electrical device structure, particularly an inductor structure for radio frequency applications, comprising:
a semiconductor substrate;
a dielectric layer structure thereon;
an electrical device on top of the dielectric layer structure; and
a cavity structure in the semiconductor substrate, where the upper boundary of the cavity structure is defined by the dielectric layer structure, and where the cavity structure has a lateral extension comparable to that of the electrical device, and is arranged underneath the electrical device to decrease the electrical coupling between the electrical device and the substrate.
The cavity structure comprises at least one air-filled space; and the dielectric layer structure includes a plurality of through holes, said through holes being plugged by dielectric material.
In a preferred version, the cavity structure comprises a plurality of air-filled spaces and at least one portion of semiconductor substrate material extending to the dielectric layer structure for supporting the dielectric layer structure mechanically, where the portion of semiconductor substrate material separates at least two of the plurality of air-filled spaces.
According to a third aspect of the present invention there is provided an integrated circuit, particularly an integrated circuit for radio frequency applications, which comprises the electrical device structure according to the second aspect of the invention.
The residual silicon substrate support provides for a mechanically strong structure, where still a silicon removal area-utilization factor of more than 90% is obtained, i.e. more than 90% of the silicon substrate material beneath the inductor is removed and replaced by air, which has a very low dielectric constant. Thus, the quality factor and self-resonance frequency of the inductor are considerably improved.
Further, there is an object of the present invention to provide a method of etching and measuring etched depth non-destructively.
According to a fourth aspect of the present invention there is thus provided a method of etching and measuring etched depth non-destructively, comprising the steps of:
providing a semiconductor substrate;
forming a dielectric layer above the substrate;
forming a plurality of through holes in the dielectric layer;
removing semiconductor substrate material under the dielectric layer by means of isotropic etching using the dielectric layer provided with through holes as hardmask, thus forming a cavity in the semiconductor substrate;
providing the ratio between the etch rate of the isotropic etching in the semiconductor substrate material in a horizontal and in a vertical direction, respectively;
optically and non-destructively measuring the horizontal distance from an outermost one of the through holes to an edge of the cavity through the dielectric layer; and
estimating the etched depth, i.e. the etched distance in the vertical direction, from the provided etch ratio and the measured horizontal distance.
Further advantages and characteristics of the present invention will be disclosed in the following detailed description of embodiments.